Memory cells of dynamic random access memories (DRAMs) generally comprise a storage capacitor and a selection transistor. An item of information to be stored is stored in the storage capacitor in the form of an electrical charge, which represents a logic value 0 or 1. By driving the read-out or selection transistor via a word line, said information can be read out via a bit line. Use is made, in particular, of memory cells in which the selection transistor is realized as a field effect transistor with a first source/drain region, a second source/drain region, a conductive channel arranged between the first and second source/drain regions, and also a gate electrode.
The gate electrode is usually driven via the word line, and, by applying a suitable voltage to the gate electrode, it is possible to control the conductivity in the channel in such a way that a current flows between the first and second source/drain regions, whereas no current flows if no gate voltage is applied.
If the selection transistor is designed as a so-called double gate transistor, that is to say if a gate electrode is in each case arranged along the conductive channel on two opposite sides, the conductivity of the channel can be controlled particularly well. On the one hand, a maximum electrostatic control of the channel is achieved, as a result of which short-channel effects can also advantageously be suppressed; on the other hand, undesirable influences of adjacent lines or gate electrodes can be shielded, and the subthreshold slope of the transistor becomes smaller.
FIG. 7 illustrates a memory cell arrangement of DRAM memory cells in which the selection transistor is in each case realized as a double gate field effect transistor, in a so-called folded bit line architecture. In FIG. 7, a multiplicity of memory cells 97 are arranged in cell rows and cell columns. Each memory cell 97 comprises a storage capacitor 6 and also a selection transistor 9 connected to one of the capacitor electrodes. Each selection transistor 9 is realized as a double gate field effect transistor with two gate electrodes 2, 25. The memory cells 97 are arranged in the manner of a checkerboard pattern, the selection transistors 9 being assigned to first arrays that are diagonally adjacent to one another and the storage capacitors 6 being assigned to diagonally adjacent second arrays situated in between. A multiplicity of word lines WL1, WL2, WL3 are arranged parallel to one another in plan view. In this case, each of the word lines WL1, WL2, WL3 comprises two drive lines 96A, 96B which respectively drive the first and the second gate electrode 2, 25.
Bit lines BL1, BL1/, BL2, BL2/ are arranged perpendicular to the word lines, which bit lines run parallel to one another in plan view and are connected to the second source/drain regions of the memory cells 97. If, by way of example, the information in the storage capacitor 6 of the memory cell 97 which is situated at the crossover point between bit line BL1 and word line WL3 is then intended to be read out, a suitable voltage is applied to the word line WL3. To put it more precisely, a voltage is applied to the drive line 96A of the word line WL3, while a corresponding countervoltage is applied to the drive line 96B of the word line WL3. In this case, voltage and countervoltage are dimensioned in such a way that the channel of the selection transistor is switched to the conductive state. As a consequence, the charge stored in each of the memory cells 97 situated along the word line WL3 is transmitted to the corresponding sense amplifiers 91 via the bit lines BL1, BL2. At the same time, reference signals or dummy signals are transmitted via the adjacent bit lines BL1/, BL2/. The reference or dummy signals are signals which are transmitted if no stored information is read out from the memory cells connected to the bit lines BL1/, BL2/.
The sense amplifier 91 forms a difference from the signals transmitted via the bit lines BL1, BL1/, as a result of which interfering influences due to noise, for example, can be eliminated. The bit lines BL1/, BL2/ thus serve as reference lines during the read-out of the bit lines BL1, BL2, and vice versa.
In the case of known memory cells, the drive lines for the second gate electrode 25 and the drive line 96A for the first gate electrode of adjacent cell columns are accommodated in a word line trench 20. That is to say that two gate electrodes are arranged in a word line trench, which gate electrodes are associated with memory cells of different cell columns and therefore have to be electrically insulated from one another. This has proved to be technologically difficult to realize. Moreover, the overlap capacitance of the two word lines becomes very high on account of their close proximity.
Therefore, there is a need to provide a memory cell arrangement in which the selection transistors are realized as double gate transistors, which, however, can be fabricated by simpler methods compared with the known ones and the function of which is more reliable. There is also a need for a method for operating a memory cell arrangement of this type.